Synopsys has just released the first complete solution for the PCIe 6.0 (PCI Express 6.0) connection interface.
During this week, Synopsys introduced the industry's first complete IP PCIe 6.0 solution, allowing chipmakers to integrate through the 5nm compute node.
The company's DesignWare IP package for PCIe 6.0 includes a driver (Synopsys interface or optional ARM AMBA 5/4/3 AXI interfaces), a physical interface (PHY), and a verification IP. This allows chipmakers to introduce the PCIe 6.0 IP and physical interface into their 5nm design and then pass the due process of verification.
The PCI Express 6.0 interface is going to offer a great increase in bandwidth. Up to 128GB / s on a x16 interface, in each direction. In theory, this will allow the PCIe 6.0 interface to be capable of transferring data at up to 256GB / s.
The controller fully supports data transfer rates of up to 64 GT / s per pin, twice that of PCIe 5.0 and four times the 16 GT / s of the current PCIe 4.0 interface.
PCIe 6.0 is also adding a number of additional features such as four-level pulse width modulation (PAM4), FLIT mode, forward error correction (FEC), and L0p power state. Synopsis also managed to reduce the required power consumption by 20% on chip-to-chip interfaces.
It is early to anticipate when we will be able to see processors, motherboards or other components that can take advantage of the PCI Express 6.0 interface on the PC, when we still cannot enjoy the PCIe 5.0 interface. We will keep you informed.
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