Many details are being revealed about AMD's Zen 4 server processors, which will support the AVX-512 instruction set and BFloat16. Additionally, they will support other ISA extensions that have not been detailed, but what is clear is that Intel Xeon Sapphire Rapids will have a great rival.
It seems that AMD will put all the meat on the grill with these EPYC Genoa processors, which will come with Zen 4 architecture and a 5nm process made by, presumably, TSMC. However, "the red devil" steps up and will offer support for the AVX-512 instruction set on these chips, a detail that was only offered by Intel on servers.
AMD Zen 4 will come with AVX-512 and BFloat16 support
The great news is that, and so it has been leaked through the ChipHell forum, from which many exclusives emerge. Apparently, they have uploaded what would be a slide that contains the specifications of the Zen 4 cores, as well as the news of the chips.
Since the birth of EPYC, Intel gave support to the set of instructions AVX-512 number to their processors Ice Lake, Cascade Lake, Cooper Lake, and even Tiger Lake; yes, we only saw that support in professional processors.
If you wonder "why didn't AMD add this support sooner," it turns out that this set of instructions was owned by Intel since 2013, the first time it applied them to its Xeon CPUs.
AVX (Advanced Vector Extension) refers to the set of instructions that serve as an extension to the IA-32 (x86) set. It has always been said that AVX was a more developed set than its rivals. In this case, we refer to the AVX-512 set, which is a series of extensions for the AVX2 operands, being able to work with registers of up to 512-bits.
On the other hand, Zen 4 will also add support for BFloat16 (Brain Floating Point Format), which is a floating-point number format that was proposed by Google. Basically, its origin lies in the artificial intelligence "Google Brain", which was created by the Google research group.
So, AVX-512 and BFloat16 in Zen 4 may be the keys that AMD wants to maximize the capabilities of its processors, taking advantage of Deep Learning and Artificial Intelligence. We've seen AI work wonders in terms of calculations and then translated into performance. A quick example is NVIDIA DLSS.
With all this, the news refers expressly to EPYC Genoa, not to all AMD Ryzen Zen 4 processors. So, we cannot claim that mainstream processors, APUs, and notebooks will support these instructions. In the case of Intel, we only see such support in the professional ranges, so we do not know what benefits it would have if AMD incorporates it in the consumer ranges.
Regarding EPYC, we will see a very extensive catalog of processors, with a maximum option of 96 cores and 192 threads, starting from 64 cores. We will have an SP5 socket, leaving SP3 behind, as these chips will support DDR5 and PCIe 5.0.
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