AMD Instinct MI200 is codenamed Aldebaran and appears to be confirmed to have multi-chip design
A few days ago information appeared indicating that AMD was working on an MCM chart. The AMD Instinct MI200 solution would be an accelerator for data centers with a modular design. Now more data has appeared about this graphics card. It would be the first graphics card on the market with a multi-chip GPU design.
AMD Instinct MI200 could launch its first multi-chip GPU in July
If there is something to admit to AMD, it is that they were right with the modular design of the Ryzen processors. Initially, they came with many problems, but they have been corrected over time. Now it seems that the company will bring this design to professional graphics cards.
The AMD Instinct MI200 would be based on CDNA architecture, use the RNDA version for the professional segment. The code name for this solution would be Aldebaran, which is the name of a giant star in the constellation Taurus.
The codename of your graphics cards is usually quite random. Usually, AMD offers developers the ability to make different suggestions. In the end, it would have won the suggestion of an AMD Linux developer, made a year ago.
We also have a patch for Linux from AMD that gives some touches regarding these graphics. Aldebaran would make use of HBM2E memories, a more advanced standard than Arcturus' HBM memories. HBM2E memories offer up to 16GB per stack, which is double that of Arcturus.
Additionally, the patch reveals that AMD Aldebaran has fewer System Direct Memory Access (SDMA) engines. These engines are used for data transfer via PCIe or XGMI / Infinity Cache interfaces. Specifically, the SDMA XGMI is reduced from 6 engines (Arcturus) to 3 engines (Aldebaran)
There is even a clarification from one of the code developers. There they talk about the die control of the solution, which suggests that we would have several dies (DIE).
Arcturus and Aldebaran difference
| ARCTURUS | ALDEBARAN |
| .asic_family = CHIP_ARCTURUS, .asic_name = "arcturus" .max_pasid_bits = 16, .max_no_of_hqd = 24, .doorbell_size = 8, .ih_ring_entry_size = 8 * sizeof (uint32_t), .event_interrupt_class = & event_interrupt_class_v9, .num_of_watch_points = 4, .mqd_size_aligned = MQD_SIZE_ALIGNED, .supports_cwsr = true, .needs_iommu_device = false, .needs_pci_atomics = false, .num_sdma_engines = 2, .num_xgmi_sdma_engines = 6, .num_sdma_queues_per_engine = 8, | .asic_family = CHIP_ALDEBARAN, .asic_name = "aldebaran", .max_pasid_bits = 16, .max_no_of_hqd = 24, .doorbell_size = 8, .ih_ring_entry_size = 8 * sizeof (uint32_t), .event_interrupt_class_points = event_interrupt_class_points = 4watchdwatch_interrupt_class_points. MQD_SIZE_ALIGNED, .supports_cwsr = true, .needs_iommu_device = false, .needs_pci_atomics = false, .num_sdma_engines = 2, .num_xgmi_sdma_engines = 3, .num_sdma_queues_per_engine = 8, |
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